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Lattice Semiconductor
Figure 2-2. Core Block Diagram for the 1G or SGMII Configurable Options
rxmac_clk
txmac_clk
cpu_if_gbit_en
Functional Description
txd
txen
txer
reset_n
tx_fifodata
tx_fifoavail
tx_fifoeof
tx_fifoempty
tx_sndpaustim
tx_sndpausreq
tx_fifoctrl
tx_staten
tx_macread
tx_statvec
tx_done
tx_disfrm
rx_fifo_full
rx_write
rx_dbout
Receive and
Transmit MAC
G/MII
Host
Interface
rxdv
rxd
rxer
col**
crs**
hcs_n
haddr
hdatain
hdataout
hwrite_n
hread_n
hready_n
hdataout_en_n
hclk
rx_stat_vector
rx_stat_en
ignore_next_pkt
rx_eof
mdc
rx_error
rx_fifo_error
rxmac_clk_en*
Management
Interface
mdo
mdio_en
mdi
txmac_clk_en*
* These inputs are only present for the SGMII Easy Connect option.
** These inputs are not present for the Gigabit MAC option.
Functional Overview
The TSMAC IP core transmits and receives data between a client application and an Ethernet network. The main
function of the Ethernet MAC is to ensure that the Media Access rules specified in the 802.3 IEEE standard are met
while transmitting and receiving Ethernet frames. Figure 2-3 , Figure 2-4 , and Figure 2-5 show some of the frame
formats of data transmitted and received on the Ethernet network that the TSMAC IP core supports.
On the receiving side, the Ethernet MAC extracts the different components of a frame and transfers them to higher
applications through the client FIFO interface.
The data received from the G/MII interface is first buffered until sufficient data is available to be processed by the
Receive MAC (Rx MAC). The Preamble and the Start-of-Frame Delimiter (SFD) information are then extracted
from the incoming frame to determine the start of a valid frame. The Receive MAC checks the address of the
received packet and validates whether the frame can be received before transferring it into the FIFO. Only valid
frames are transferred into the FIFO (runts and fragments are discarded). The Rx MAC also provides a statistics
vector on a per packet basis that can be used by the application. The TSMAC IP core always calculates CRC to
check whether the frame was received error-free.
On the transmit side, the Tx MAC is responsible for controlling access to the physical medium. The Tx MAC reads
data from an external client Tx FIFO, formats this data into an Ethernet packet and passes it to the G/MII module.
IPUG51_03.0, December 2010
9
Tri-Speed Ethernet MAC User’s Guide
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